1. Field of the Invention
The present invention relates to a system for tracing a program by detecting coincidence between an address which has previously been set and the execution address in its central processing unit (CPU).
2. Description of the Prior Art
First of all, a conventional tracing system, for example, the one which has been utilized for debugging a computer program will be described hereinbelow.
In FIG. 1, reference numeral 1 designates a CPU, and numeral 2 designates a usual tracing system for checking whether the execution address in the CPU 1 coincides with a preset address or not. The CPU 1 involves a memory address register 3, the contents of which are outputted to the tracing system 2 as the next address signal. The tracing system 2 comprises a trace address register 4, a comparator 5, and a trace controller 6. The trace address register 4 has the function to store the address to be traced, and the contents thereof are supplied to the comparator 5 as the trace address signal. The comparator 5 compares the next address (NEXT AD) signal supplied from the memory address register 3 of the CPU 1 with the trace address signal, and an equivalent signal indicating the detection of coincidence is outputted in the case where both the next address signal and the trace address signal coincide with each other. The resulting equivalent signal is inputted to the trace controller 6. When the equivalent signal is received, the trace controller 6 effects at least one operation which has previously been determined. Such operations may be indication of coincidence between the execution address and the trace address, setting the next address required for tracing into the trace address register 4, and stoppage of operation of the CPU.
FIG. 2 is a flow chart in respect of a part of program involved in the CPU illustrating such sequence in which addresses set in the memory address register 3 are successively updated in accordance with orders such as 99, 100, 101, . . . , and 104, whereby prescribed contents, i.e., instructions M0, M1, M2, M3 and M4 are successively read out from a memory (not shown) in response to these addresses. In this case, it is assumed that a program is branched so as to execute the contents corresponding to the address 103 where the instruction M1 read out in the address 100 is smaller than the contents Acc of an accumulator (not shown) of the CPU, namely such condition Acc&gt;M1 is satisfied. Accordingly, even if the program has been branched by means of execution of the instruction M1 in the case where the contents of the trace address register 4 are address 101, there is a case where coincidence between the next address signal and the trace address signal is detected by the comparator 5 to output equivalent signal, whilst the program executes the contents corresponding to address 103 in the case where the contents of the memory address register 3 come to be address 101. Thus, in such conventional tracing system, there is such a case where such malfunction that coincident signal is outputted even if the trace address does not coincide with execution address of the CPU dependent on the form of the program performed.